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Introduction to Semiconductor Device Physics

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Lecture 2 Images from Chapter 2

Many ceramics



Alumina Diamond Inorganic Glasses Mica Polypropylene PVDF PET SiO2 Soda silica glass Borosilicate Amorphous As2Se3 Pure SnO2 Intrinsic Si Te Graphite NiCr Ag Metals

Degenerately Doped Si


Intrinsic GaAs












Conductivity (½ m)-1

Range of conductivites exhibited by various materials

Fig 2.25

From Principles of Electronic Materials and Devices, Third Edition, S.O. Kasap (© McGraw-Hill, 2005)

Grain1 Grain2

Grain Boundary
(a) (b)

(a ) Gra in bounda rie s ca use sca tte ring of the e le ctron a nd the re fore a dd to the re sistivity by Ma tthie sse n's rule . (b) For a ve ry gra iny solid, the e le ctron is sca tte re d from gra in bounda ry to gra in bounda ry a nd the me a n fre e pa th is a pproxima te ly e qua l to the me a n gra in dia me te r.
From Principles of Electronic Materials and Devices, Third Edition, S.O. Kasap (© McGraw-Hill, 2005)

Fig 2.32


Hillock Grain boundary Void

Void and failure


Current Interconnect Grain boundary

ce terfa In Hot




(a) Electrons bombard the metal ions and force them to slowly migrate (b) Formation of voids and hillocks in a polycrystalline metal interconnect by the electromigration of metal ions along grain boundaries and interfaces. (c) Accelerated tests on 3 mm CVD (chemical vapor deposited) Cu line. T = 200 oC, J = 6 MA cm-2: void formation and fatal failure (break), and hillock formation.
|SOURCE: Courtesy of L. Arnaud et al, Microelectronics Reliability, 40, 86, 2000.
Fig 2.38 From Principles of Electronic Materials and Devices, Third Edition, S.O. Kasap (© McGraw-Hill, 2005)

Three levels of interconnects in a flash memory chip. Different levels are connected through vias.
|SOURCE: Courtesy of Dr. Don Scansen, Semiconductor Insights, Kanata, Ontario, Canada From Principles of Electronic Materials and Devices, Third Edition, S.O. Kasap (©


Low permittivity dielectric M3

M5 M4 M3 M2 M1

Cu interconnects
M2 M1


Metal interconnects wiring devices on a silicon crystal. Three different metallization levels M1, M2, and M3 are used. The dielectric between the interconnects has been etched away to expose the interconnect structure.
|SOURCE: Courtesy of IBM

Cross section of a chip with 7 levels of metallization, M1 to M7. The image is obtained with a scanning electron microscope (SEM).
|SOURCE: Courtesy of Mark Bohr, Intel.

From Principles of Electronic Materials and Devices, Third Edition, S.O. Kasap (©

Simple Depiction of Dual Damascene Metal Process

Green: dielectric separation layers Red: etch stop layer (Missing: diffusion-barrier thin film around metal Cu)…...

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